High-Frequency Integrated CircuitsA transistor-level, design-intensive overview of high speed and high frequency monolithic integrated circuits for wireless and broadband systems from 2 GHz to 200 GHz, this comprehensive text covers high-speed, RF, mm-wave, and optical fibre circuits using nanoscale CMOS, SiGe BiCMOS, and III-V technologies. Step-by-step design methodologies, end-of chapter problems, and practical simulation and design projects are provided, making this an ideal resource for senior undergraduate and graduate courses in circuit design. With an emphasis on device-circuit topology interaction and optimization, it gives circuit designers and students alike an in-depth understanding of device structures and process limitations affecting circuit performance. |
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Índice
| 1 | |
| 14 | |
| 77 | |
Highfrequency devices | 142 |
Circuit analysis techniques for highfrequency integrated circuits | 318 |
Tuned power amplifier design | 374 |
Lownoise tuned amplifier design | 439 |
Broadband lownoise and transimpedance amplifiers | 503 |
Mixers switches modulators and other control circuits | 553 |
Design of voltagecontrolled oscillators | 621 |
Highspeed digital logic | 698 |
Highspeed digital output drivers with waveshape control | 756 |
SoC examples | 803 |
Trigonometric identities | 851 |
Index | 892 |
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Palavras e frases frequentes
65nm CMOS amplifier amplitude antenna bandwidth bias current biased bipolar broadband Calculate capacitance capacitor cascode channel CMOS CMOS technology collector current density current source defined device differential pair diode drain driver efficiency emitter length employed equation equivalent circuit feedback filter first fMAX frequency function GaAs gate fingers gate width Gilbert cell HEMT high-frequency IEEE illustrated in Figure impedance matching inductive inductor input impedance integrated circuits layout linearity load low-noise matching network maximum mixer mm-wave modulation MOSFET n-MOSFET nanoscale noise current noise impedance noise parameters noise temperature operation optimal optimum noise oscillator output power parasitic phase noise phased array power gain receiver resistance resistor resonator S-parameters schematic shown in Figure SiGe BiCMOS SiGe HBT silicon simulation small signal substrate switch tail current topology transceiver transconductance transistor transmitter tuned two-port varactor Voinigescu voltage swing
